1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device which internally generates a burst mode control signal.
2. Description of the Related Art
Generally, memory devices are characterized by their addressing mode. One addressing mode is burst mode. In a burst mode memory device, a read/write operation is performed on an initial externally supplied address along with a number of successive addresses where the successive addresses are internally generated. To internally generate the successive addresses, a counter is used where the number of successive addresses can be adjusted by an external control signal.
Typically, a burst address advance ADV signal is used to request burst mode operation. The ADV signal is generated by a central processing unit (CPU) and is used to advance an internal burst counter in order to control burst access after an initial address is loaded. When the ADV signal is not active, the internal burst counter will not increment and the address will not advance.
In burst mode, a burst mode memory device 202 typically receives the ADV signal from a CPU 201 as shown in FIG. 1. CPU 201 also generates other memory control signals, such as a Synchronous Address Status from Cache Controller signal ADSC or a Synchronous Address Status from Processor signal ADSP, which control read and write and read operations. The ADSC signal is used to load internal address registers with new addresses. (Note that where the ADSC signal is referred to throughout the specification, the reference equally applies to an ADSP signal.) A chip enable signal CE is used to enable the memory device. A read latency signal RL is used along with the burst mode control signal ADV to start the read/write operation. When the ADV signal for memory device 202 is generated by CPU 201, then an ADV pulse can only be generated at fixed intervals in the CPU execution cycle. As a result, the intervals at which the ADV signal can be generated is limited by the CPU.